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description the A8515 is a multi-output white led (wled) driver for lcd backlighting in consumer and industrial displays. it integrates a current-mode boost converter with an internal power dmos switch and two current sinks. the boost converter can drive up to 24 leds: 12 leds per string at 120 ma. the led sinks can be paralleled together to achieve higher led currents, up to 240 ma. the A8515 can operate from a single power supply, from 5 to 40 v. pwm dimming is implemented with an external pwm input signal. the en/pwm dimming pin is used to control the led intensity by using pulse width modulation. the low, 720 mv regulation voltage on the led current sources reduces power loss and improves efficiency. the A8515 is provided in a 16-pin tssop package (suffix lp) with an exposed thermal pad. it is lead (pb) free, with 100% matte tin leadframe plating. A8515-ds, rev. 2 features and benefits ? wide input voltage range: 5 to 40 v ? maximum led current of 120 ma ? tssop-16 (lp) package; exposed pad offers best-in-class thermal performance ? typical led accuracy of 0.5%, and 0.5% for led-to-led matching ? internal bias supply for single-supply operation (typically between v in = 8 to 24 v) ? integrated boost converter with 60 v dmos switch with overvoltage protection (ovp) ? drives up to 12 series leds in 2 parallel strings ? single en/pwm pin interface for both pwm dimming and enable function ? sync function to synchronize boost converter switching frequencies up to 2.3 mhz, this gives the designer the ability minimize component size ? provides driver for external pmos input disconnect switch ? protection features: ? open or shorted v led pin protection ? open schottky protection ? cycle-by-cycle current limit ? overtemperature protection (otp) ? output short circuit protection wide input voltage range, high efficiency fault tolerant led driver typical application diagram not to scale A8515 package: 16-pin tssop with exposed thermal pad (suffix lp) applications ? desktop lcd flat panel displays (fpd) ? flat panel video displays ? lcd tvs and monitors figure 1. typical application circuit; 12 v input, output to 20 leds (10 series leds in each of two strings) at 120 ma each. gate sw ovp v out 10 leds each string r ovp r z c z c p vsense vin vdd en/pwm apwm iset fset agnd pgnd comp led2 led1 fault pad A8515 150 v c nc 10 h 158 k 100 k r iset 8.25 k r fset 10 k c out 4.7 f 50 v c in 4.7 f/ 50 v c vdd 0.1 f 0.47 f d1 l1 120 pf v in 10 to 14 v 2 a / 60 v
wide input voltage range, high efficiency fault tolerant led driver A8515 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating unit ledx pin ?0.3 to 55 v ovp pin ?0.3 to 60 v vin, vsense, gate pins v sense should not exceed v in by more than 0.4 v. gate cannot exceed v in by more than 0.4 .v ?0.3 to 40 v sw pin continuous ?0.6 to 62 v t < 50 ns ?1.0 v f a u l t pin ?0.3 to 40 v iset, fset, apwm, comp pins ?0.3 to 5.5 v all other pins ?0.3 to 7 v operating ambient temperature t a range g ?40 to 105 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the elec trical characteristics table is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reli ability. selection guide part number packing A8515glptr-t 4000 pieces per 13-in. reel thermal characteristics may require derating at maximum conditions characteristic symbol test conditions* value unit package thermal resistance r ja on 4-layer pcb based on jedec standard 34 oc/w on 2-layer pcb with 1 in. 2 of copper area each side 52 oc/w *additional thermal information available on the allegro website
wide input voltage range, high efficiency fault tolerant led driver A8515 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vdd pgnd ovp sw gate vsense vin fault led2 led1 agnd iset fset/sync en/pwm apwm comp 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pad pin-out diagram terminal list table number name function 1 vdd output of internal ldo; connect a 0.1 f decoupling capacitor between this pin and gnd. 2 pgnd power ground for internal nmos device. 3 ovp this pin is used to sense an overvoltage condition; connect the r ovp resistor from v out to this pin to adjust the overvoltage protection function (ovp). 4 sw the drain of the internal nmos switch of the boost converter. 5 gate output gate driver pin for external p-channel fet control. 6 vsense connect this pin to the negative sense side of the current sense resistor r sc ; the threshold voltage is measured as v in ? v sense . 7 vin input power to the A8515 as well as the positive input used for the current sense resistor. 8 f a u l t this pin is used to indicate a fault condition, it is an open drain type configuration that will be pulled low when a fault occurs; connect a 100 k resistor between this pin and the required logic level voltage. 9 comp output of the error amplifier and compensation node; connect a series r z c z network from this pin to gnd for control loop compensation. 10 apwm analog trimming option or dimming; applying a digital pwm signal to this pin adjusts the internal i set current. 11 en/pwm pwm dimming pin used to control the led intensity by using pulse width modulation; the typical pwm dimming frequency is in the range of 200 hz to 1 khz. 12 fset/sync frequency/synchronization pin; connect a resistor r fset from this pin to gnd to set the switching frequency. this pin can also be used to synchronize two or more converters in the system; the maximum synchronization frequency is 2.3 mhz. 13 iset connect the r iset resistor between this pin and gnd to set the led 100% current level. 14 agnd led signal ground. 15 led1 connect the cathode of the led string to this pin. 16 led2 connect the cathode of the led string to this pin. ?pad exposed pad of the package providing enhanced thermal dissipation; this pad must be connected to the ground plane(s) of the pcb with at least 8 thermal vias, directly in the pad.
wide input voltage range, high efficiency fault tolerant led driver A8515 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram vdd regulator uvlo internal soft start enable pwm thermal shutdown open/short led detect iset fault led driver 1.235 v ref driver circuit internal v cc internal v cc v ref internal v cc v ref v ref i ss i ss i adj goff 100 k agnd current sense input current sense amplifier pmos driver diode open sense ovp sense oscillator sw vin fset/sync comp vsense gate en/pwm apwm pgnd agnd iset ovp led1 led2 fault agnd pgnd + ? + ? + ? + ? + ?
wide input voltage range, high efficiency fault tolerant led driver A8515 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com continued on the next page? electrical characteristics 1 valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit input voltage specifications operating input voltage range 3 v in 5 ? 40 v uvlo start threshold v uvlorise v in rising ? ? 4.35 v uvlo stop threshold v uvlofall v in falling ? ? 3.90 v uvlo hysteresis 4 v uvlohys ? 450 ? mv input currents input quiescent current i q en/pwm = v ih ; sw = 2 mhz, no load ? 5.5 ? ma input sleep supply current i qsleep v in = 16 v, en/pwm = sync = 0 v ? 2 10.0 a input logic levels (en/pwm, apwm) input logic level-low v il v in throughout operating input voltage range ? ? 400 mv input logic level-high v ih v in throughout operating input voltage range 1.5 ? ? v en/pwm pin open drain pull-down resistor r enpwm ? 100 ? k apwm pull-down resistor r apwm en/pwm = v ih ? 100 ? k apwm apwm frequency f apwm apwm, v ih = 1.5 v, v il = 0.4 v 20 ? 1000 khz error amplifier open loop voltage gain a vol ? 48 ? db transconductance g m i comp = 10 a ? 990 ? a/v source current i ea(src) v comp = 1.5 v ? ?350 ? a sink current i ea(sink) v comp = 1.5 v ? 350 ? a comp pin pull-down resistance r comp f a u l t = 1 ? 2000 ? overvoltage protection overvoltage threshold v ovp(th) ovp connected to v out 7.7 8.1 8.5 v ovp sense current i ovph 188 199 210 a ovp leakage current i ovplkg r ovp = 40.2 k , v in = 16 v, en/pwm = v il ? 0.1 1 a secondary overvoltage protection v ovp(sec) ? 55 ? v boost switch switch on-resistance r sw i sw = 0.750 a, v in = 16 v ? 300 ? m switch leakage current i swlkg v sw = 16 v, en/pwm = v il ? 0.1 1 a switch current limit i sw(lim) 3.0 3.5 4.2 a secondary switch current limit 4 i sw(lim2) higher than i sw(lim) (max) for all conditions, device latches when detected ? 7 ? a soft start boost current limit i swss(lim) initial soft start current for boost switch ? 700 ? ma minimum switch on-time t swontime ? 85 ? ns minimum switch off-time t swofftime ? 47 ? ns
wide input voltage range, high efficiency fault tolerant led driver A8515 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com oscillator frequency oscillator frequency f sw r fset = 10 k 1.8 2 2.2 mhz r fset = 20 k ? 1 ? mhz r fset = 35.6 k ? 580 ? khz fset/sync pin voltage v fset r fset = 10 k ? 1.00 ? v fset frequency range f fset 580 ? 2500 khz synchronization synchronized pwm frequency f swsync 580 ? 2300 khz synchronization input minimum off-time t pwsyncoff 150 ?? ns synchronization input minimum on-time t pwsyncon 150 ?? ns sync input logic voltage v sync(h) fset/sync pin, high level ?? 0.4 v v sync(l) fset/sync pin, low level 2.0 ?? v led current sinks ledx accuracy err led i set = 120 a ? 0.5 2 % ledx matching ledx i set = 120 a ? 0.5 1 % ledx regulation voltage v led v led1 = v led2 , i set = 120 a ? 720 ? mv i set to i ledx current gain a iset i set = 120 a 960 980 1000 a/a iset pin voltage v iset ? 1.003 ? v allowable iset current i set 40 ? 125 a v led short detect v ledsc while led sinks are in regulation, sensed from ledx pin to gnd 4.6 ?? v soft start ledx current i ledss current through each enabled ledx pin during soft start ? 3.2 ? ma maximum pwm dimming until off-time t pwml measured while en/pwm = low, during dimming control and internal references are powered-on (exceeding t pwml results in shutdown) ? 32,750 ? f sw cycles minimum pwm on-time t pwmh first cycle when powering-up device ? 0.75 2 s en/pwm high to led-on delay t dpwm(on) time between pwm enable and led current reaching 90% of maximum ? 0.5 1 s en/pwm low to led-off delay t dpwm(off) time between pwm enable going low and led current reaching 10% of maximum ?? 500 ns gate pin gate pin sink current i gsink v gs = 0 v with respect to v in ?? 104 ? a gate fault shutdown t gfault ?? 3 s gate voltage v gs gate to source voltage measured when gate is on ? -6.7 ? v electrical characteristics 1 (continued) valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver A8515 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 (continued) valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit vsense pin vsense pin sink current i adj 18.8 20.3 21.8 a vsense trip point v sensetrip measured between vin and vsense, r adj = 0 ? 180 ? mv f a u l t pin f a u l t pull-down voltage v fault i fault = 1 ma (400 ) ?? 0.5 v f a u l t pin leakage current i faultlkg v fault = 5 v ?? 1 a thermal protection (tsd) thermal shutdown threshold 4 t sd temperature rising ? 165 ? oc thermal shutdown hysteresis 4 t sdhys ? 20 ? oc 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2 typical specifications are at t a = 25oc. 3 minimum v in = 5 v is only required at startup. after startup is completed, the ic is able to function down to v in = 4 v. 4 ensured by design and characterization, not production tested.
wide input voltage range, high efficiency fault tolerant led driver A8515 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 7.7 7.6 7.8 7.9 8.0 8.1 8.2 8.3 8.4 v ovp(th) (v) 190 192 194 196 198 200 202 204 206 208 210 i ovph ( a) 3.60 3.61 3.62 3.63 3.64 3.65 3.66 3.67 3.68 3.69 3.70 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 f sw (mhz) switching frequency ovp pin sense current ovp pin overvoltage threshold 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 v uvlorise (v) v uvlofall (v) 0 1 2 3 4 5 6 7 8 9 10 i qsleep ( a) vin input sleep mode current versus ambient temperature vin uvlo start threshold voltage vin uvlo stop threshold voltage versus ambient temperature versus ambient temperature versus ambient temperature versus ambient temperature versus ambient temperature temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) temperature (c)
wide input voltage range, high efficiency fault tolerant led driver A8515 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 20.0 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 i adj ( a) vsense pin sink current 0 0.2 0.4 0.6 0.8 1.0 1.2 err led (%) led current setpoint accuracy -6.9 -6.8 -6.7 -6.6 -6.5 -6.4 -6.3 v gs (v) input disconnect switch voltage gate to source 119.0 119.2 119.4 119.6 119.8 120.0 120.2 i led (ma) i set = 120 a -0.5 -0.3 -0.1 0.1 0.3 0.5 $ ledx (%) led to led matching accuracy 960 965 970 975 980 985 990 995 1000 a iset temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) iset to led current gain versus ambient temperature versus ambient temperature led current versus ambient temperature versus ambient temperature versus ambient temperature versus ambient temperature
wide input voltage range, high efficiency fault tolerant led driver A8515 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 100 95 90 85 80 75 70 65 60 e ? ciency (%) 100 95 90 85 80 75 70 65 60 e ? ciency (%) 100 95 90 85 80 75 70 65 60 e ? ciency (%) input voltage, v in (v) e ? ciency for various led con gura ti ons i led = 80 ma, led v f 3.2 v e ? ciency for various led con gura ti ons i led = 100 ma, led v f 3.2 v e ? ciency for various led con gura ti ons i led = 120 ma, led v f 3.2 v input voltage, v in (v) input voltage, v in (v) 5.5 7.0 8.5 10.0 13.0 16.0 11.5 14.5 5.5 7.0 8.5 10.0 13.0 16.0 11.5 14.5 5.5 7.0 8.5 10.0 13.0 16.0 11.5 14.5 2 strings, 6 series leds each 2 strings, 7 series leds each 2 strings, 8 series leds each 2 strings, 6 series leds each 2 strings, 7 series leds each 2 strings, 8 series leds each 2 strings, 6 series leds each 2 strings, 7 series leds each 2 strings, 8 series leds each
wide input voltage range, high efficiency fault tolerant led driver A8515 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the A8515 incorporates a current-mode boost controller with internal dmos switch, and two led current sinks. it can be used to drive two led strings of up to 12 white leds in series, with current up to 120 ma per string. for optimal efficiency, the output of the boost stage is adaptively adjusted to the minimum voltage required by both led strings. this is expressed by the following equation: v out = max ( v led1 , v led2 ) + v reg (1) where v ledx is the voltage drop across led string 1 and 2, and v reg is the regulation voltage of the led current sinks (typi- cally 0.72 v at the maximum led current). enabling the ic the ic turns on when a logic high signal is applied on the en/pwm pin with a minimum duration of t pwmh for the first clock cycle, and the input voltage present on the vin pin is greater than the 4.35 v necessary to clear the uvlo (v uvlorise ) threshold. the power-up sequence is shown in figure 2. before the leds are enabled, the A8515 driver goes through a system check to determine if there are any possible fault conditions that might prevent the system from functioning correctly. also, if the fset pin is pulled low, the ic will not power-up. more informa- tion on the fset pin can be found in the sync section of this datasheet. powering up: led pin short-to-gnd check the vin pin has a uvlo function that prevents the A8515 from powering-up until the uvlo threshold is reached. after the vin pin goes above uvlo, and a high signal is present on the en/pwm pin, the ic proceeds to power-up. as shown in figure 3, at this point the A8515 enables the disconnect switch and checks if any led pins are shorted to gnd and/or are not used. if an ledx pin is shorted to ground the A8515 will not proceed with soft start until the short is removed from the ledx pin. this prevents the A8515 from powering-up and putting an uncon- trolled amount of current through the leds. the various detect scenarios are presented on the next page, in figures 4a to 4c. the led detect phase starts when the gate voltage of the disconnect switch is equal to v in ? 4.5 v. after the voltage threshold on the ledx pins exceeds 120 mv, a delay of between 3000 and 4000 clock cycles is used to determine the status of the pins. thus, the led detection duration varies with the switching frequency, as shown in the following table: switching frequency (mhz) detection time (ms) 2 1.5 to 2 1 3 to 4 0.800 3.75 to 5 0.600 5 to 6.7 functional description figure 2. power-up diagram; shows vdd (ch1, 2 v/div.), fset (ch2, 1 v/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 2 v/div.) pins, 200 s/div. figure 3. power-up diagram; shows the relationship of an ledx pin with respect to the gate voltage of the disconnect switch (if used) during the led detect phase, as well as the duration of the led detect phase for a switching frequency of 2 mhz; shows gate (ch1, 5 v/div.), iled (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 5 v/div.) pins, 500 s/div. t vdd en/pwm fset iset c1 c3 c4 c2 t gate gate = v in ? 4.5 v led detection period en/pwm ledx iset c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8515 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the led pin detection voltage thresholds are as follows: led pin voltage led pin status action <70 mv short-to-gnd power-up is halted 150 mv not used led removed from operation >325 mv led pin in use none all unused pins should be connected with a 1.54 k resistor to gnd, as shown in figure 5. the unused pin, with the pull-down resistor, will be taken out of regulation at this point and will not contribute to the boost regulation loop. 4a. an led detect occurring when both led pins are selected to be used; shows led1 (ch1, 500 mv/div.), led2 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 5 v/div.) pins, 500 s/div. 4b. example with led2 pin not being used; the detect voltage is about 150 mv; shows led1 (ch1, 500 mv/div.), led2 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 5 v/div.) pins, 500 s/div. 4c. example with one led shorted to gnd. the ic will not proceed with power- up until the shorted led pin is released, at which point the led is checked to see if it is being used; shows led1 (ch1, 500 mv/div.), led2 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 5 v/div.) pins, 1 ms/div. . figure 5. channel select setup: (left) using only channel led1, (right) using both channels. gnd 1.54 k A8515 led1 led2 led1 led2 gnd A8515 t led detection period en/pwm led2 led1 iset c1 c3 c4 c2 t pin shorted short removed en/pwm led2 led1 iset c1 c3 c4 c2 t led detection period en/pwm led2 led1 iset c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8515 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 f sw (mhz) resistance for r set (k ) 10.0 30.0 20.0 12.5 32.5 22.5 17.5 15.0 25.0 35.0 soft start function during soft start the ledx pins are set to sink (i ledss ) and the boost switch current is reduced to the i swss(lim) level to limit the inrush current generated by charging the output capacitors. when the converter senses that there is enough voltage on the led pins the converter proceeds to increase the led current to the preset regulation current and the boost switch current limit is switched to the i sw(lim) level to allow the A8515 to deliver the necessary output power to the leds. this is shown in figure 7. frequency selection the switching frequency on the boost regulator is set by the resis- tor connected to the fset pin, and the switching frequency can be can be anywhere from 580 khz to 2.3 mhz. figure 6 shows the typical switching frequencies, in mhz, for given resistor values, in k . if during operation a fault occurs that will increase the switch- ing frequency, the fset pin is clamped to a maximum switching frequency of no more than 3.5 mhz. if the fset pin is shorted to gnd the part will shut down. for more details see the fault mode table later in this section. sync the A8515 can also be synchronized using an external clock on the sync pin. figure 8 shows the correspondence of a sync sig- nal and the fset pin, and figure 9 shows the result when a sync signal is detected: the led current does not show any variation while the frequency changeover occurs. at power-up if the fset pin is held low, the ic will not power-up. only when the fset pin is tri-stated to allow for the pin to rise, to about 1 v, or when a sync clock is detected, will the A8515 try to power-up. figure 7. startup diagram showing the input current, output voltage, and output current; shows i out (ch1, 200 ma/div.), i in (ch2, 1 a/div.), v out (ch3, 20 v/div.), and en/pwm (ch4, 5 v/div.), 1 ms/div. figure 6. typical switching frequency versus value of r fset resistor. figure 9. transition of the sw waveform when the sync pulse is detected. the A8515 switching at 2 mhz, applied sync pulse at 1 mhz; shows v out (ch1, 20 v/div.), i led (ch2, 200 ma/div.), fset (ch3, 2 v/div.), and sw node (ch4, 20 v/div.), 5 s/div. t inrush current caused by enabling the disconnect switch (when used) operation during i swss(lim) normal operation i sw(lim) en/pwm i in i out v out c1 c3 c4 c2 t sw node fset i led v out c1 c3 c4 c2 figure 8. diagram showing a synchronized fset pin and switch node; shows v out (ch1, 20 v/div.), i led (ch2, 200 ma/div.), fset (ch3, 2 v/div.), and sw node (ch4, 20 v/div.), 2 s/div. t sw node 2 mhz operation 1 mhz operation fset i led v out c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8515 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the basic requirement of the sync signal is 150 ns minimum on- time and 150 ns minimum off time, as indicated by the specifica- tions for t pwsyncon and t pwsyncoff . figure 9 shows the timing for a synchronization clock into the A8515 at 2.2 mhz. thus any pulse with a duty cycle of 33% to 66% at 2.2 mhz can be used to synchronize the ic. the rise and fall edges should be about 10 ns. the sync pulse duty cycle ranges for selected switching fre- quencies are: sync pulse frequency (mhz) duty cycle range (%) 2.2 33 to 66 2 30 to 70 1 15 to 85 0.800 12 to 88 0.600 9 to 91 if during operation a sync clock is lost, the ic will revert to the preset switching frequency that is set by the resistor r fset . dur- ing this period the ic will stop switching for a maximum period of about 7 s to allow the sync detection circuitry to switch over to the externally preset switching frequency. if the clock is held low for more than 7 s, the A8515 will shut down. in this shutdown mode the ic will stop switching, the input disconnect switch is open, and the leds will stop sinking current. to shut- down the ic into low power mode, the user needs to disable the ic using the en/pwm pin, by keeping the pin low for a period of 65 ms. if the fset pin is released at any time after 5 s, the A8515 will proceed to soft start. led current setting and led dimming the maximum led current can be up to 120 ma per channel, and is set through the iset pin. to set the i led current, connect a resistor, r iset , between this pin and gnd, according to the fol- lowing formula: r iset = 980 / i led (2) where i led is in a and r iset is in . this sets the maximum cur- rent through the leds, referred to as the 100% current . standard r iset values, at gain equals 980, are as follows: standard closest r iset resistor value (k ) led current per led, i led (ma) 8.25 120 9.76 100 12.1 80 15.0 65 pwm dimming the led current can be reduced from the 100% current level by pwm dimming using the en/pwm pin. when the en/pwm pin is pulled high, the A8515 turns on and all enabled leds sink 100% current. when en/pwm is pulled low, the boost converter and led sinks are turned off. the compensation (comp) pin is floated, and critical internal circuits are kept active. the typical pwm dimming frequencies fall between 200 hz and 1 khz. fig- ures 12a to 12d provide examples of pwm switching behavior. another important feature of the A8515 is the pwm signal to led current delay. this delay is typically less than 500 ns, which allows greater accuracy at low pwm dimming duty cycles, as shown in figure 11. 150 ns 150 ns t = 454 ns 154 ns t pwsyncon t pwsyncoff figure 10. sync pulse on and off time requirements. figure 11. percentage error of the led current versus pwm duty cycle (at 200 hz pwm frequency). 10 8 6 4 2 0 err led (%) pwm duty cycle, d (%) 0.1 1 10 100 worst-case typical
wide input voltage range, high efficiency fault tolerant led driver A8515 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 12a. typical pwm diagram showing v out , i led , and comp pin as well as the en/pwm signal. pwm dimming frequency is 500 hz at 50% duty cycle; shows v out (ch1, 10 v/div.), comp (ch2, 2 v/div.), en/pwm (ch3, 5 v/div.), and i led (ch4, 100 ma/div.), 500 s/div. figure 12b. typical pwm diagram showing v out , i led , and comp pin as well as the en/pwm signal. pwm dimming frequency is 500 hz at 1% duty cycle ; shows v out (ch1, 10 v/div.), comp (ch2, 2 v/div.), en/pwm (ch3, 5 v/div.), and i led (ch4, 100 ma/div.), 500 s/div. figure 12c. delay from rising edge of en/pwm signal to led current; shows en/pwm (ch1, 2 v/div.), and i led (ch2, 50 ma/div.), 200 ns/div. figure 12d. delay from falling edge of en/pwm signal to led current turn off; shows en/pwm (ch1, 2 v/div.), and i led (ch2, 50 ma/div.), 200 ns/div. t i led en/pwm comp v out c1 c3 c4 c2 t i led en/pwm c1 c2 t i led en/pwm c1 c2 t i led en/pwm comp v out c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8515 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com apwm pin the apwm pin is used in conjunction with the iset pin. this is a digital signal pin that internally adjusts the iset current. the typical input signal frequency is between 20 khz and 1 mhz. the duty cycle of this signal is inversely proportional to the percent- age of current that is delivered to the leds (figure 14). as an example, a system that delivers a full led current of 120 ma per led would deliver 90 ma of current per led when an apwm signal is applied with a duty cycle of 25%. when this pin is not used it should be tied to gnd. to use this pin for a trim function, the user should set the maxi- mum output current to a value higher than the required current by at least 5%. the led iset current is then trimmed down to the figure 13. simplified block diagram of the apwm iset block. figure 16. diagram showing the transition of led current from 120 ma to 90 ma, when a 25% duty cycle signal is applied to the apwm pin; en/pwm = 1; shows i led (ch1, 50 ma/div.), apwm (ch2, 5 v/div.), and en/pwm (ch3, 5 v/div.), 500 s/div. figure 17. diagram showing the transition of led current from 90 ma to 120 ma, when a 25% duty cycle signal is removed from the apwm pin. en/pwm = 1; shows i led (ch1, 50 ma/div.), apwm (ch2, 5 v/div.), and en/pwm (ch3, 5 v/div.), 500 s/div. figure 14. output current versus duty cycle; 200 khz apwm signal. figure 15. percentage error of the led current versus pwm dut y cycle; 200 khz apwm signal. apwm current adjust iset current mirror led driver iset en/pwm A8515 150 100 50 0 i out (ma) pwm duty cycle, d (%) 04060 20 80 100 ?15 ?10 ?5 0 pwm duty cycle, d (%) 04060 20 80 100 err led (%) t i led apwm en/pwm c1 c3 c2 t i led apwm en/pwm c1 c3 c2
wide input voltage range, high efficiency fault tolerant led driver A8515 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com appropriate value. another consideration that also is important is the limitation of the user apwm signal duty cycle. in some cases it might be preferable to set the maximum iset current to be 25% to 50% higher, thus allowing the apwm signal to have duty cycles that are between 25% and 50%. although the apwm dimming function has a wide frequency range, if this function is used strictly as an analog dimming function it is recommended to use frequency ranges between 50 and 500 khz for best accuracy. the frequency range must be considered only if the user is not using this function as a closed loop trim function. another limitation is that the propagation delay between this apwm signal and i out takes several milli- seconds to change the actual led current. this effect is shown in figures 16 through 18. analog dimming the A8515 can also be dimmed by using an external dac or another voltage source applied either directly to the ground side of the r iset resistor or through an external resistor to the iset pin (see figure 19). ? for a single resistor (upper panel of figure 19), the iset current is controlled by the following formula: i set = v iset ? v dac r iset ? v dac (3) where v iset is the iset pin voltage and v dac is the dac out- put voltage. when the dac voltage is equal to v iset , the internal reference, there is no current through r iset . when the dac voltage starts to decrease, the iset current starts to increase, thus increasing the led current. when the dac voltage is 0 v, the led current will be at its maximum. ? for a dual-resistor configuration (lower panel of figure 19), the iset current is controlled by the following formula: i set = ? v iset r iset v dac ? v iset r 1 (4) the advantage of this circuit is that the dac voltage can be higher or lower, thus adjusting the led current to a higher or lower value of the preset led current set by the r iset resistor: ? vdac = 1.003 v; the output is strictly controlled by r iset ? vdac > 1.003 v; the led current is reduced ? vdac < 1.003 v; the led current is increased figure 18. transition of output current level when a 50% duty cycle signal is applied to the apwm pin, in conjunction with a 50% duty cycle pwm dimming being applied to the en/pwm pin; shows i out (ch1, 100 ma/div.), apwm (ch2, 5 v/div.), and en/pwm (ch3, 5 v/div.), 1 ms/div. t i out apwm en/pwm c1 c3 c2 figure 19. simplified diagrams of voltage control of i led : typical applications using a dac to control i led using a single resistor (upper), and dual resistors (lower). gnd dac vdac gnd A8515 iset gnd dac vdac gnd A8515 iset r iset r1 r iset
wide input voltage range, high efficiency fault tolerant led driver A8515 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com led short detect both ledx pins are capable of handling the maximum v out that the converter can deliver, thus providing protection from the led pin to v out in the event of a connector short. an led pin that has a voltage exceeding v ledsc will be removed from operation (see figure 20). this is to prevent the ic from dissipating too much power by having a large voltage pres- ent on an ledx pin. while the ic is being pwm-dimmed, the ic rechecks the dis- abled led every time the en/pwm signal goes high, to prevent false tripping of an led short event. this also allows some self- correction if an intermittent led pin short-to-v out is present. overvoltage protection the A8515 has overvoltage protection (ovp) and open schottky diode protection. the ovp protection has a default level of 8 v and can be increased up to 55 v by connecting r ovp between the ovp pin and v out . when the current into the ovp pin exceeds 199 a typical, the ovp comparator goes low and the boost stops switching. the following equation can be used to determine the resistance for setting the ovp level: r ovp = ( v outovp ? v ovp(th) ) / i ovph (5) where: v outovp is the target overvoltage level, r ovp is the value of the external resistor, in , v ovp(th) is the pin ovp trip point found in the electrical charac- teristics table, and i ovph is the current into the ovp pin. there are several possibilities for why an ovp condition would be encountered during operation, the two most common being: a disconnected output, and an open led string. examples of these are provided in figures 21 and 22. figure 20. example of the disabling of an led string when the led pin voltage is increased above 4.6 v; shows i out (ch1, 200 ma/div.), led1 (ch2, 5 v/div.), and en/pwm (ch3, 5 v/div.), 10 s/div. t i out led1 en/pwm c1 c3 c2
wide input voltage range, high efficiency fault tolerant led driver A8515 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 21 illustrates when the output of the A8515 is discon- nected from load during normal operation. the output voltage instantly increases up to ovp voltage level and then the boost stops switching to prevent damage to the ic. if the output is drained off, eventually the boost might start switching for a short duration until the ovp threshold is hit again. figure 22 displays a typical ovp event caused by an open led string. after the ovp condition is detected, the boost stops switching, and the open led string is removed from operation. afterwards v out is allowed to fall, and eventually the boost will resume switching and the A8515 will resume normal operation. A8515 also has built-in secondary overvoltage protection to protect the internal switch in the event of an open diode condi- tion. open schottky diode detection is implemented by detecting overvoltage on the sw pin of the device. if voltage on the sw pin exceeds the device safe operating voltage rating, the A8515 disables and remains latched. to clear this fault, the ic must be shut down either by using the en/pwm signal or by going below the uvlo threshold on the vin pin. figure 23 illustrates this. as soon as the switch node voltage (sw) exceeds 60 v, the ic shuts down. due to small delays in the detection circuit, as well as there being no load present, the switch node voltage will rise above the trip point voltage. figure 24 illustrates when the A8515 is being enabled during an open diode condition. the ic goes through all of its initial led detection and then tries to enable the boost, at which point the open diode is detected. figure 21. ovp protection in an output disconnect event; shows v out (ch1, 10 v/div.), sw node (ch2, 50 v/div.), en/pwm (ch3, 5 v/div.), and i led (ch4, 200 ma/div.), 1 ms/div. figure 23. ovp protection in an open schottky diode event, while the ic is in normal operation; shows en/pwm (ch1, 5 v/div.), sw node (ch2, 50 v/ div.), v out (ch3, 20 v/div.), and i led (ch4, 200 ma/div.), 1 s/div. figure 22. ovp protection in an open led string event; shows v out (ch1, 10 v/div.), sw node (ch2, 50 v/div.), en/pwm (ch3, 5 v/div.), and i led (ch4, 200 ma/div.), 500 s/div. figure 24. ovp protection when the ic is enabled during an open diode condition; shows en/pwm (ch1, 5 v/div.), sw node (ch2, 50 v/div.), v out (ch3, 10 v/div.), and i led (ch4, 200 ma/div.), 500 s/div. t v out en/pwm sw node output disconnect event detected i led c1 c3 c4 c2 t v out en/pwm sw node open diode condition detected i led c1 c3 c4 c2 t v out en/pwm sw node open diode condition detected i led c1 c3 c4 c2 t v out en/pwm sw node i led c1 c3 c4 c2 led string open condition detected
wide input voltage range, high efficiency fault tolerant led driver A8515 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com boost switch overcurrent protection the boost switch is protected with cycle-by-cycle current limiting set at a minimum of 3.0 a. there is also a secondary current limit that is sensed on the boost switch. when detected this current limit immediately shuts down the A8515. the level of this cur- rent limit is set above the cycle-by-cycle current limit to protect the switch from destructive currents when the boost inductor is shorted. various boost switch overcurrent conditions are shown in figures 25 through 27. figure 25. normal operation of the switch node (sw); inductor current (i l ) and output voltage (v out ) for 9 series leds in each of 2 strings configuration; shows sw node (ch1, 20 v/div.), i l (ch2, 1 a/div.), v out (ch3, 10 v/div.), and en/pwm (ch4, 5 v/div.), 2 s/div. figure 26. cycle-by-cycle current limiting; inductor current (yellow trace, i l ), note reduction in output voltage as compared to normal operation with the same configuration (figure 25); shows sw node (ch1, 20 v/div.), i l (ch2, 1 a/div.), v out (ch3, 10 v/div.), and en/pwm (ch4, 5 v/div.), 2 s/div. figure 27. secondary boost switch current limit; when this limit is hit, the A8515 immediately shuts down; shows en/pwm (ch1, 5 v/div.), v out (ch2, 5 v/div.), sw node (ch3, 50 v/div.), and i l (ch4, 2 a/div.), 100 ns/div. t v out en/pwm sw node i l c1 c3 c4 c2 t v out en/pwm sw node i l c1 c3 c4 c2 t i l en/pwm sw node c1 c3 c4 c2 fault
wide input voltage range, high efficiency fault tolerant led driver A8515 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com input overcurrent protection and disconnect switch the primary function of the input disconnect switch is to protect the system and the device from catastrophic input currents during a fault condition. the external circuit implementing the discon- nect is shown in figure 28. if the input disconnect switch is not used, the vsense pin must be tied to vin and the gate pin must be left open. when selecting the external pmos, check for the following parameters: ? drain-source breakdown voltage v (br)dss > ?40 v ? gate threshold voltage (make sure it is fully conducting at v gs = -4 v, and cut-off at ?1 v) ? r ds(on) : make sure the on-resistance is rated at v gs = -4.5 v or similar, not at -10 v; derate it for higher temperature if the input current level goes above v sensetrip of the preset cur- rent limit threshold, the A8515 will shut down in less than 3 s regardless of user input (see figure 29). this is a latched condi- tion. the fault flag is also set to indicate a fault. this feature is meant to prevent catastrophic failure in the system due to a short of the inductor to gnd. setting the current sense resistor the typical threshold for the current sense circuit is 180 mv, when r adj is 0 . this voltage can be trimmed by the r adj resistor. the typical trip point should be set at about 3 a, which coincides with the cycle-by-cycle current limit minimum thresh- old. a sample calculation is done below: given: 2.85 a of input current, and the calculated maximum value of the sense resistor, r sc = 0.063 . the r sc chosen is 0.056 , a standard. also: r adj = ( v sensetrip ? v adj ) / i adj (6) the trip point voltage is calculated as: v adj = 2.85 a 0.056 = 0.160 v r adj = (0.180 ? 0.160 v) / (20.3 a) = 1.0 k figure 28. typical circuit showing the implementation of the input disconnect feature. gate r adj r sc vsense vin A8515 q1 v in figure 29. typical secondary overcurrent fault condition. i in is the input current through the switch. when the current limit is reached the A8515 disables the gate of the disconnect switch (gate); shows f a u l t (ch1, 5 v/div.), gate (ch2, 10 v/div.), i in (ch3, 2 a/div.), and en/pwm (ch4, 5 v/ div.), 5 ms/div. t gate en/pwm i in c1 c3 c4 c2 fault A8515 shuts down
wide input voltage range, high efficiency fault tolerant led driver A8515 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com input uvlo when v in and v sense rise above the v uvlorise threshold, the A8515 is enabled. A8515 is disabled when v in falls below the v uvlofall threshold for more than 50 s. this small delay is used to avoid shutting down because of momentary glitches in the input power supply. when v in falls below 4.35 v, the ic will shut down (see figure 30). vdd the vdd pin provides regulated bias supply for internal circuits. connect the capacitor c vdd with a value of 0.1 f or greater to this pin. the internal ldo can deliver no more than 2 ma of cur- rent with a typical v dd of about 3.5 v, enabling this pin to serve as the pull-up voltage for the f a u l t pin. shutdown if the en/pwm pin is pulled low for more than t pwml , the device enters shutdown mode and clears all internal fault reg- isters. as an example, at a 2 mhz clock frequency, it will take approximately 16.3 ms to shut down the ic into the low power mode (figure 31). when the A8515 is shut down, the ic will dis- able all current sources and wait until the en/pwm signal goes high to re-enable the ic. if faster shut down is required the fset pin can be used. fault protection during operation the A8515 constantly monitors the state of the system to deter- mine if any fault conditions occur during normal operation. the response to a triggered fault condition is summarized in the fault mode table, on the next page. the possible fault conditions that the device can detect are: open led pin, led pin shorted to gnd, shorted inductor, v out short to gnd, sw pin shorted to gnd, iset pin shorted to gnd, and input disconnect switch source shorted to gnd. note the following: ? some of the protection features might not be active during startup, to prevent false triggering of fault conditions. ? some of these faults will not be protected if the input disconnect switch is not being used. an example of this is vout short to ground. figure 30. shutdown showing a falling input voltage (v in ); shows v in (ch1, 2 v/div.), i out (ch2, 200 ma/div.), v dd (ch3, 5 v/div.), and en/pwm (ch4, 2 v/div.), 5 ms/div. figure 31. shutdown using the enable function, showing the 16 ms delay between the en/pwm signal and when the vdd and gate of the disconnect switch turns off; shows gate (ch1, 10 v/div.), i out (ch2, 200 ma/div.), v dd (ch3, 5 v/div.), and en/pwm (ch4, 2 v/div.), 5 ms/div. t i out en/pwm v in v dd c1 c2 c3 c4 t i out en/pwm gate v dd c2 c1 c3 c4
wide input voltage range, high efficiency fault tolerant led driver A8515 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fault mode table fault name type active fault flag set description boost disconnect switch sink driver primary switch overcurrent protection (cycle-by-cycle current limit) auto-restart always no this fault condition is triggered by the cycle-by- cycle current limit, i sw(lim) . prevents current in inductor from exceeding i sw(lim) 3.38 a (typical). off for a single cycle on on secondary switch current limit latched always yes when the current through the boost switch exceeds secondary current sw limit (i sw(lim2) ) the device immediately shuts down the disconnect switch, led drivers, and boost. the fault flag is set. to re- enable the device, the en/pwm pin must be pulled low for 32750 clock cycles. off off off input disconnect current limit latched always yes the device is immediately shut off if the voltage across the input sense resistor goes above v sensetrip . the fault flag is set. to re-enable the device the en/pwm pin must be pulled low for 32750 clock cycles. off off off secondary ovp latched always yes secondary overvoltage protection is used for open diode detection. when diode d1 opens, the sw pin voltage will increase until v ovp(sec) is reached. this fault latches the ic. the input disconnect switch is disabled as well as the led drivers, and the fault flag is set. to re-enable the part the en/pwm pin must be pulled low for 32750 clock cycles. off off off led pin short protection auto-restart startup no this fault prevents the device from starting-up if any of the ledx pins are shorted. the device stops soft-start from starting while any of the led pins are determined to be shorted. once the short is removed, soft-start is allowed to start. off on off led pin open auto-restart normal operation no when an led pin is open the device will determine which led pin is open by increasing the output voltage until ovp is reached. any led string not in regulation will be turned off. the device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. on on off for open pins. on for all others. iset short protection auto-restart always no this fault occurs when the iset current goes above 150% of the maximum current. the boost will stop switching and the ic will disable the led sinks until the fault is removed. when the fault is removed the ic will try to regulate to the preset led current. off on off continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver A8515 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fset short protection auto-restart always yes fault occurs when the fset current goes above 150% of maximum current. the boost will stop switching, the disconnect switch will turn off and the ic will disable the led sinks until the fault is removed. when the fault is removed the ic will try to restart with soft-start. off off off overvoltage protection auto-restart always no fault occurs when ovp pin exceeds v ovp(th) threshold. the A8515 will immediately stop switching to try to reduce the output voltage. if the output voltage decreases then the A8515 will restart switching to regulate the output voltage. stop during ovp event. on on led short protection auto-restart always no fault occurs when the led pin voltage exceeds 5.1 v. when the led short protection is detected the led string above the threshold will be removed from operation. on on off for shorted pins. on for all others. overtemperature protection auto-restart always no fault occurs when the die temperature exceeds the overtemperature threshold, typically 165c. off off off vin uvlo auto-restart always no fault occurs when v in drops below v uvlo , typically 3.90 v. this fault resets all latched faults. off off off fault mode table (continued) fault name type active fault flag set description boost disconnect switch sink driver
wide input voltage range, high efficiency fault tolerant led driver A8515 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com applications information design example for boost configuration this section provides a method for selecting component values when designing an application using the A8515. the resulting design is diagramed in figure 32. assumptions: for the purposes of this example, the following are given as the application requirements: ? v bat : 10 to 14 v ? quantity of led channels, # channels : 2 ? quantity of series leds per channel, # seriesleds : 10 ? led current per channel, i led : 120 ma ? v f at 120 ma: 3 to 3.6 v ? f sw : 2 mhz ? t a (max): 65c ? pwm dimming frequency: 200 hz, 1% duty cycle procedure: the procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. step 1 connect leds to pins led1 and led2. step 2 determining the led current setting resistor r iset : r iset = 1.003 980 / i led (7) = 983 / 120 ma = 8.19 k choose a 8.25 k resistor. step 3 determining the ovp resistor. the ovp resistor is connected between the ovp pin and the output voltage of the converter. step 3a the first step is determining the maximum voltage based on the led requirements. then this value and the regula- tion voltage (v led ) should be added together, as well as another 2 v to take noise and output ripple into consideration. the v led of the A8515 is 720 mv. v out(ovp) = # seriesleds v f + v led + 2 (8) = 10 3.6 v+ 2.0 v + 0.720 v = 38.72 v then the ovp resistor is: r ovp = ( v out(ovp) ? v ovp(th) ) / i ovph (9) = (38.72 v ? 8.1 v) / 199 a = 154 k where both i ovph and v ovp(th) are taken from the electrical characteristics table. chose a value of resistor that is higher value than the calculated r ovp . in this case a value of 158 k was selected. below is the actual value of the minimum ovp trip level with the selected resistor: v out(ovp) = 158 k 199 a + 8.1 v = 39.5 v step 3b at this point a quick check must be done to see if the conversion ratio is acceptable for the selected frequency. d maxofboost = 1 ? t swofftime f sw (10) = 1 ? 1.5 47 ns 2 mhz = 85.9% where minimum off time (t swofftime ) is found in the electrical characteristics table. the theoretical maximum v out is then calculated as: v outthe (max) v d =? 1 ? d maxofboost v in (min) 0.4 70.5 v == ? 1 ? 0.859 10 v (11) where v d is the diode forward voltage. a good approximation of efficiency can be taken from the efficiency curves located in this datasheet. a value of 90% is a good starting approximation. the theoretical maximum v out value must be greater than the value v out(ovp) . if this is not the case, the switching frequency of the boost converter must be reduced to meet the maximum duty cycle requirements. step 4 selecting the inductor. the inductor must be chosen such that it can handle the necessary input current. in most applica- tions, due to stringent emi requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range.
wide input voltage range, high efficiency fault tolerant led driver A8515 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 4a determining the duty cycle, calculated as follows: d (max) v d = + v in (min) v out(ovp) 74.9% == 39.5 + 0.4 1 ? 1 ? 10 v (12) step 4b determining the maximum and minimum input current to the system. the minimum input current will dictate the induc- tor value. the maximum current rating will dictate the current rating of the inductor. first, the maximum input current, given: i out = # channels i led 0.240 a == 2 0.120 a (13) then: i in (max) = v in (min) v out(ovp) i out h 1.053 a == 39.5 v 10 v 0.9 240 ma (14) where is efficiency. next, calculate minimum input current, as follows: i in (min) = v in (max) v out(ovp) i out h 0.752 a == 39.5 v 14 v 0.9 240 ma (15) a good approximation of efficiency, , can be taken from the efficiency curves located in the diode datasheet. a value of 90% is a good starting approximation. step 4c determining the inductor value. to ensure that the inductor operates in continuous conduction mode, the value of the inductor must be set such that the ? inductor ripple current is not greater than the average minimum input current. a first past assumes i ripple to be 40% of the maximum inductor current: i l = i in (max) 0.4 (16) = 1.05 a 0.4 = 0.42 a then: l = v in (min) d (max) f sw i l 8.9 h 0.42 a == 0.749 10 v 2 mhz (17) step 4d double-check to make sure the ? current ripple is less than i in (min): i in (min) > 1 / 2 i l (18) 0.75 a > 0.21 a a good inductor value to use would be 10 h. step 4e this step is used to verify that there is sufficient slope compensation for the inductor chosen. the slope compensation value is determined by the following formula: 2 10 6 slope compensation == f sw 3.6 3.6 a / s (19) next insert the inductor value used in the design: = v in (min) d (max) f sw l used i lused 10 ( h) 0.37 a == 0.75 10 (v) 2.0 (mhz) (20) calculate the minimum required slope: = (1 ? d (max)) (1 ? 0.75) f sw required slope (min) i lused 0.37 (a) 1 1 1 10 ? 6 110 ? 6 == 2.97 a/ s 2.0 (mhz) (21) if the minimum required slope is greater than the calculated slope compensation, the inductor value must be increased. note: the slope compensation value is in a/ s, and 1 10 ?6 is a constant multiplier. step 4f determining the inductor current rating. the inductor current rating must be greater than the i in (max) value plus the ripple current i l , calculated as follows: i l (max) = i in (max) + 1 / 2 i lused (22) = 1.05 a + 0.37 a / 2 = 1.24 a step 5 determining the resistor value for a particular switching frequency. use the r fset values shown in figure 7. for example, a 10 k resistor will result in a 2 mhz switching frequency. step 6 choosing the proper switching diode. the switching diode must be chosen for three characteristics when it is used in
wide input voltage range, high efficiency fault tolerant led driver A8515 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com led lighting circuitry. the most obvious two are: current rating of the diode and reverse voltage rating. the reverse voltage rating should be such that during operation condition, the voltage rating of the device is larger than the maxi- mum output voltage. in this case it is v out(ovp) . the peak current through the diode is calculated as: i dp = i in (max) + 1 / 2 i lused (23) = 1.05 a + 0.37 a / 2 = 1.24 a the third major component in deciding the switching diode is the reverse current, i r , characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding off of the output voltage, due to leakage currents. i r can be a large contributor, especially at high tempera- tures. on the diode that was selected in this design, the current varies between 1 and 100 a. step 7 choosing the output capacitors. the output capacitors must be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the biggest factors that contribute to the size of the output capacitor are: pwm dimming frequency, and pwm duty cycle. another major contributor is leakage current ( i lk ). this current is the combina- tion of the ovp leakage current as well as the reverse current of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically the volt- age variation on the output (v cout ) during pwm dimming must be less than 250 mv, so that no audible hum can be heard. the capacitance can be calculated as follows: c out = f pwm(dimming) 1 ? d (min) 1 ? 0.01 200 hz i lk 200 a 3.96 f == 0.250 v v cout (24) a capacitor larger than 3.96 f should be selected due to degra- dation of capacitance at high voltages on the capacitor. a ceramic 4.7 f 50 v capacitor is a good choice to fulfill this requirement. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l the rms current through the capacitor is given by: i cout rms = 1 ? d (max) d (max) + ? i lused i out 0.240 a 0.42 a 12 == i in (max) 1 ? 0.75 0.75 + 0.37 1.05 12 (25) the output capacitor must have a current rating of at least 420 ma. the capacitor selected in this design was a 4.7 f 50 v capacitor with a 1.5 a current rating. step 8 selecting input capacitor. the input capacitor must be selected such that it provides a good filtering of the input voltage waveform. a good rule of thumb is to set the input voltage ripple v in to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 0.37 a ? i lused 0.23 f 8 == ? v in 2 mhz 0.1 v 8 (26)
wide input voltage range, high efficiency fault tolerant led driver A8515 28 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 32. the schematic diagram showing calculated values from the design example above the rms current through the capacitor is given by: i in rms = (1 ? d (max)) i out ? i lused 0.10 a 12 = = i in (max) (1 ? 0.75) 0.240 0.37 1.05 12 (27) a good ceramic input capacitor with ratings of 2.2 f 50v or 4.7 f 50 v will suffice for this application. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l step 9 choosing the input disconnect switch components. set the input disconnect current limit to 3 a by choosing a sense resistor. the calculated maximum value of the sense resistor is: r sc (max) = v sensetrip / 3.0 a (28) = 0.180 v / 3.0 a= 0.060 the r sc chosen is 0.056 , a standard value. the trip point voltage must be: v adj = 3.0 a 0.056 = 0.168 v r adj = ( v sensetrip ? v adj ) / i adj (29) r adj = (0.180 v ? 0.168 v) / 20.3 a = 591 a value of 590 was selected for this design. gate sw ovp r ovp vsense vin vdd c vdd c p c z r z en/pwm apwm iset fset agnd pgnd comp led2 led1 fault pad A8515 150 v c 10 h 158 k r adj 590 r sc 0.056 c in 2.2 f / 50 v d1 2 a / 60 v q1 l1 100 k r fset 10 k r iset 8.25 k 4.7 f 50 v 0.1 f 0.47 f 120 pf v out 10 leds each string v in 10 to 14 v
wide input voltage range, high efficiency fault tolerant led driver A8515 29 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com design example for sepic configuration this section provides a method for selecting component values when designing an application using the A8515 in sepic (sin- gle-ended primary-inductor converter) circuit. sepic topology has the advantage that it can generate a positive output voltage either higher or lower than the input voltage. the resulting design is diagrammed in figure 33. assumptions: for the purposes of this example, the following are given as the application requirements: ? v bat : 6 to 14 v ( v in (min): 5 v and v in (max): 16 v ) ? quantity of led channels, # channels : 2 ? quantity of series leds per channel, # seriesleds : 4 ? led current per channel, i led : 120 ma ? led v f at 120 ma: 3.3 v ? f sw : 2 mhz ? t a (max): 65c ? pwm dimming frequency: 200 hz, 1% duty cycle procedure: the procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. step 1 connect leds to pins led1 and led2. if only one of the led channels is needed, the unused ledx pin should be pulled to ground using a 1.5 k resistor. step 2 determining the led current setting resistor r iset : r iset = ( v iset a iset ) / i led (30) = (1.003 (v) 980) / 0.120 (a) = 8.19 k choose an 8.25 k 1% resistor (or 16.2 k if led current is 60 ma/channel). step 3 determining the ovp resistor. the ovp resistor is connected between the ovp pin and the output voltage of the converter. step 3a the first step is determining the maximum voltage based on the led requirements. the regulation voltage, v led , of the A8515 is 720 mv. a constant term, 2 v, is added to give margin to the design due to noise and output voltage ripple. v out(ovp) = # seriesleds v f + v led + 2 (v) (31) = 4 3.3 (v) + 0.72 (v) + 2 (v) = 15.9 v then the ovp resistor is: r ovp = ( v out(ovp) ? v ovp(th) ) / i ovph (32) = (15.9 (v) ? 8.1 (v)) / 0.199 (ma) = 39.196 k where both i ovph and v ovp(th) are taken from the electrical characteristics table. in this case a value of 39.2 k was selected. below is the actual value of the minimum ovp trip level with the selected resistor: v out(ovp) = 39.2 (k ) 0.199 (ma) + 8.1 (v) = 15.9 v step 3b at this point a quick check must be done to determine if the conversion ratio is acceptable for the selected frequency. d max = 1 ? t swofftime f sw (33) = 1 ? 1.5 47 (ns) 2 (mhz) = 85.9% where the minimum off-time (t swofftime ) is found in the electri- cal characteristics table. the theoretical maximum v out is then calculated as: v out (max) = v d ? 1 ? d max d max v in (min) 0.4 (v) 30.3 v == ? 1 ? 0.86 0.86 5 (v) (34) where v d is the diode forward voltage. the theoretical maximum v out value must be greater than the value v out(ovp) . if this is not the case, it may be necessary to reduce the frequency to allow the boost to convert the volt- age ratios. step 4 selecting the inductor. the inductor must be chosen such that it can handle the necessary input current. in most applica-
wide input voltage range, high efficiency fault tolerant led driver A8515 30 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com tions, due to stringent emi requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range. step 4a determining the duty cycle, calculated as follows: d (max) v d = + v d + v out(ovp) + v in (min) v out(ovp) 76.5% == 5 (v) + 15.9 (v) + 0.4 (v) + 0.4 (v) 15.9 (v) (35) step 4b determining the maximum and minimum input current to the system. the minimum input current will dictate the induc- tor value. the maximum current rating will dictate the current rating of the inductor. first, the maximum input current, given: i out = # channels i led 0.240 a == 2 120 (ma) (36) then: i in (max) = v in (min) v out(ovp) i out h 0.848 a == 15.9 (v) 5 (v) 0.90 0.24 (a) (37) where is efficiency. next, calculate minimum input current, as follows: i in (min) = v in (max) v out(ovp) i out h 0.265 a == 15.9 (v) 16 (v) 0.90 0.24 (a) (38) step 4c determining the inductor value. to ensure that the inductor operates in continuous conduction mode, the value of the inductor must be set such that the ? inductor ripple current is not greater than the average minimum input current. as a first pass assume i ripple to be 30% of the maximum inductor current: i l = i in (max) i ripple (39) = 0.848 0.30 = 0.254 a then: l = v in (min) d (max) f sw i l 7.53 h 0.254 (a) = = 0.765 5 (v) 2 (mhz) (40) step 4d double-check to make sure the ? current ripple is less than i in (min): i in (min) > 1 / 2 i l (41) 0.265 a > 0.127 a a good inductor value to use would be 10 h. step 4e next insert the inductor value used in the design to determine the actual inductor ripple current: = v in (min) d (max) f sw l used i lused 10 ( h) 0.191 a == 0.765 5 (v) 2 (mhz) (42) step 4f determining the inductor current rating. the inductor current rating must be greater than the i in (max) value plus half of the ripple current i l , calculated as follows: l (min) = i in (max) + 1 / 2 i lused (43) = 0.848 (a) + 0.096 (a) = 0.944 a step 5 determining the resistor value for a particular switching frequency. use the r fset values shown in figure 6. for example, a 10 k resistor will result in an 2 mhz switching frequency. step 6 choosing the proper switching diode. the switching diode must be chosen for three characteristics when it is used in led lighting circuitry. the most obvious two are: current rating of the diode and reverse voltage rating.
wide input voltage range, high efficiency fault tolerant led driver A8515 31 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the reverse breakdown voltage rating for the output diode in a sepic circuit should be: v bd > v out(ovp) (max) + v in (max) (44) > 15.9 (v) + 16 (v) = 31.9 v because the maximum output voltage in this case is v out(ovp) . the peak current through the diode is calculated as: i dp = i in (max) + 1 / 2 i lused (45) = 0.848 (a) + 0.096 (a) = 0.944 a the third major component in deciding the switching diode is the reverse current, i r , characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding off of the output voltage, due to leakage currents. i r can be a large contributor, especially at high tempera- tures. on the diode that was selected in this design, the current varies between 1 and 100 a. it is often advantageous to pick a diode with a much higher breakdown voltage, just to reduce the reverse current. therefore for this example, pick a diode rated for a v bd of 60 v, instead of just 40 v. step 7 choosing the output capacitors. the output capacitors must be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the biggest factors that contribute to the size of the output capacitor are: pwm dimming frequency and pwm duty cycle. another major contributor is leakage current, i lk . this current is the combina- tion of the ovp leakage current as well as the reverse current of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically, the volt- age variation on the output, v cout , during pwm dimming must be less than 250 mv, so that no audible hum can be heard. the capacitance can be calculated as follows: c out = f pwm(dimming) 1 ? d (min) 1 ? 0.01 200 (hz) i lk 200 ( a) 3.96 f == 0.250 (v) v cout (46) a capacitor larger than 3.96 f should be selected due to degra- dation of capacitance at high voltages on the capacitor. select a 4.7 f capacitor for this application. the rms current through the capacitor is given by: i cout rms = 1 ? d (max) d (max) i out 0.240 (a) 0.433 a == 1 ? 0.765 0.765 (47) the output capacitor must have a ripple current rating of at least 500 ma. the capacitor selected for this design is a 4.7 f 50 v capacitor with a 1.5 a current rating. step 8 selecting input capacitor. the input capacitor must be selected such that it provides a good filtering of the input voltage waveform. a estimation rule is to set the input voltage ripple, v in , to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 0.191 (a) ? i lused 0.24 f 8 == ? v in 2 (mhz) 0.05 (v) 8 (48) the rms current through the capacitor is given by: c in rms = ? i lused 0.055 a 12 = = 0.191 (a) 12 (49) a good ceramic input capacitor with a rating of 2.2 f 25 v will suffice for this application.
wide input voltage range, high efficiency fault tolerant led driver A8515 32 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 9 selecting coupling capacitor c sw . the minimum capaci- tance of c sw is related to the maximum voltage ripple allowed across it: c sw = f sw 0.24 (a) 0.765 i out d max 0.92 f == ? v sw 2 (mhz) 0.1 (v) (50) the rms current requirement of the coupling capacitor is given by: i csw rms = 1 ? d (max) d (max) i in (max) 0.848 (a) 0.47 a == 1 ? 0.765 0.765 (51) the voltage rating of the coupling capacitor must be greater than v in (max), or 16 v in this case. a ceramic capacitor rated for 2.2 f 25 v will suffice for this application. figure 33. typical application showing sepic configuration, with accurate input current sense, and vsense to gnd protection gate sw ovp vsense vin vdd en/pwm apwm iset fset agnd pgnd comp led2 led1 fault r ovp l2 pad A8515 r z c z v c 39.2 k 120 pf 0.056 590 10 h 10 h 8.25 k 150 0.47 f 0.1 f 10 k r sc c sw r adj c in c out c vdd q1 l1 r1 100 k 2.2 f / 25 v 2.2 f / 25 v 4.7 f 50 v d1 2 a / 60 v r fset r iset c p v out v in 6 to 14 v
wide input voltage range, high efficiency fault tolerant led driver A8515 33 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 16-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 16x 0.65 bsc 0.25 bsc 2 1 16 5.000.10 4.400.10 6.400.20 gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 abt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b c exposed thermal pad (bottom surface); dimensions may vary with device 6.10 0.65 0.45 1.70 3.00 3.00 16 2 1 reference land pattern layout (reference ipc7351 sop65p640x110-17m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view c branded face 3 nom 3 nom
wide input voltage range, high efficiency fault tolerant led driver A8515 34 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2010-2011, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 2 december 15, 2011 update to application examples, add v sync

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